Field Effect Transistor (FET) is a three-terminal device in which the current through two terminals (drain and source) is controlled by a voltage at a third terminal (gate). FET is a unipolar device, that is, the current involves only majority carriers. One variant of the FET is a Junction FET (JFET) in which the control (gate) voltage varies the depletion width of a reverse-biased p-n junction. A similar device results if the p-n junction is replaced by a reverse-biased Schottky barrier by placing a metal gate electrode directly on the semiconductor. Such a device is called a metal-semiconductor FET (a MESFET). Typically, the MESFET is formed on an n-type GaAs layer grown epitaxially on a semi-insulating substrate and may or may not include other layers such as a buffer layer, positioned between the substrate and the n-type layer, or a contact layer, positioned between the n-type layer and ohmic drain and source contacts. A Schottky barrier gate is formed on top of the n-type GaAs layer. By reverse-biasing or forward-biasing the Schottky gate, the channel can be depleted or opened to a desired current level.
By using GaAs instead of Si, a higher electron mobility is available and GaAs can be operated at higher temperatures and, therefore, higher power levels. Close geometric tolerances can be achieved, and the MESFET can be very small, with gate lengths L&lt;1.mu.m being common. This is important at high frequencies, since drift time and capacitances must be kept to a minimum.
One of the enduring problems in GaAs MESFET technology, however, is the relatively low Schottky barrier height .phi..sub.B) of metals used for the gate contact. On the n-type GaAs the .phi..sub.B is basically insensitive to the metal used, with the values being typically in the range 0.71-0.8 eV. This is a limiting factor in the design of many GaAs circuits and the availability of a contact with a large barrier height would allow fabrication of digital logic circuits with better noise margins. Some applications of GaAs MESFET technology would benefit from an increase in the relatively low Schottky barrier height (.phi..sub.B) of metals used for the gate contact. A further advantage would be the relaxed requirement on the uniformity of threshold voltage of the component MESFETs.
A number of different approaches to increasing the Schottky barrier height have been attempted. For example, an incorporation of a thin fully-depleted p-type layer under the gate contract on n-GaAs leads to an enhancement of the .phi..sub.B. Values up to 1.33 eV have been demonstrated using 50 .ANG. thick C or Zn delta-doped p type layers (.about.6-7.times.10.sup.19 cm.sup.-3) epitaxially grown on the n-type GaAs. See S. J. Eglash et al., Journal of applied Physics, Vol. 61, No. 11, 1 Jun. 1987, pp. 5159-5169. Another approach consists of depositing a thin interfacial layer of Si or other materials between the n-type GaAs and the metal contact. Barrier heights of 1 eV have been demonstrated by this technique. See J. R. Waldrop and R. W. Grant, Appl. Phys. Lett., Vol. 52, No. 21, (23 May 1988) p. 1794-1796. However, these techniques complicate the manufacture of MESFETs and may bring unexpected undesirable effects.
The role of a thin layer of native oxide, e.g. of the order of 20-25 .ANG. in thickness, in degrading the properties of alloyed ohmic contacts on GaAs has been widely recognized; however, less attention has been paid to its effects on Schottky contacts. Woodall's effective work function model, see J. M. Woodall and J. L. Freeouf, J. Vac. Sci. Technol., Vol. 21, No. 2, (July/August 1982) pp. 574-576, suggests that the Fermi level at the interface is not fixed by surface states but rather is related to work functions of microclusters of one or more interfacial phases resulting from either oxygen contamination or metal-semiconductor reactions which occur during metallization. Thus, with an oxide-free interface, the Schottky barrier height of a metal contact should be dependent on the metal work function.